Regviz

Espressif Systems /ESP32-P4 /PCNT /INT_ENA

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INT_ENA

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-P4/PCNT/INT_ENA#0x0

31282724232019161512118743000000000000000000000000000000000000000000 (CNT_THR_EVENT_U0_INT_ENA)CNT_THR_EVENT_U0_INT_ENA0 (CNT_THR_EVENT_U1_INT_ENA)CNT_THR_EVENT_U1_INT_ENA0 (CNT_THR_EVENT_U2_INT_ENA)CNT_THR_EVENT_U2_INT_ENA0 (CNT_THR_EVENT_U3_INT_ENA)CNT_THR_EVENT_U3_INT_ENA

Description

Interrupt enable register

Fields

CNT_THR_EVENT_U0_INT_ENA

The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
CNT_THR_EVENT_U1_INT_ENA

The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
CNT_THR_EVENT_U2_INT_ENA

The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
CNT_THR_EVENT_U3_INT_ENA

The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data